When it comes to processor architectures, you're probably familiar with x86 and ARM, but have you ever heard of RISC-V? If not, you owe it to yourself to learn something about this up and coming technology that I expect will become more widely used in the future.
I'll explain RISC-V — but first, let's talk ISAs. An Instruction Set Architecture or ISA is an abstract model of a computer architecture, defining such things as the register model and machine code instructions. A realization of an ISA, such as a Central Processing Unit (CPU), is called an implementation. Widely used ISAs include x86 and ARM, older systems like SPARC and VAX, and early microprocessors like the Z80 and 6502.
What is not as widely known is that ISAs are intellectual property that is licensed. So, for example, a manufacturer like Freescale or Broadcom that wishes to design an ARM-compatible processor needs to license it from Arm Ltd., the owners of the ISA.
While you can certainly design your own ISA, it is not a trivial undertaking as it involves specifying the behavior of the machine in great detail. The x86 architecture, for example, originally dates back to the Intel 8086 chip released in 1978. The Arm architecture started with the BBC Micro developed by Acorn Computers in 1981. Both ISAs have continued to be improved and extended.
What is RISC-V?
Pronounced "risk-five," RISC-V is an ISA based on reduced instruction set computer (RISC) principles. Unlike most other ISA designs, it is provided under a open source license that does not require fees to use.
The project started in 2010 at the University of California, Berkeley along with volunteer contributors not affiliated with the university. To give the project stability and make it attractive to commercial users, a formal RISC-V Foundation was incorporated to own, maintain and publish the RISC-V definition. It was recently renamed RISC-V International, incorporated in Switzerland.
Why is it Important?
On a technical level, RISC-V doesn't incorporate any innovative or new features. It follows established RISC principles and uses a load-store architecture. An advantage of this is that it doesn't violate any known patents.
Like many other ISAs, the specification defines different levels of instruction sets. This include 32 and 64-bit variants, and extensions to support floating point instructions. This allows versions to be developed that are suited to a range of applications from small embedded microcontrollers to desktop personal computers and supercomputers with vector processors.
RISC-V is supported by a number of language compilers, including the GNU Compiler Collection (GCC), a popular free-software compiler, and by the Linux operating system (both 32 and 64-bit).
A number of companies are offering or have announced RISC-V hardware. These range from microcontrollers to SOMs and SOCs that can run Linux, and FPGAs that can include a RISC-V core.
A few notable products include:
RISC-V is significant because it will allow smaller device manufacturers to build hardware without paying royalties and allow developers and researchers to design and experiment with a proven and freely available instruction set architecture. This will encourage innovation and competition at a time when many large manufacturers are buying up their competitors, such as the recent acquisition of Arm Ltd by Nvidia.